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mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 1 description the mitsubishi mobile flash m5m29gb/t160bvp are 3.3v-only high speed 16,777,216-bit cmos boot block flash memories with alternating bgo (back ground operation) feature. the bgo feature of the device allows program or erase operations to be perform ed in one bank while the device simultaneously allows read operations to be performed on the other bank. this bgo feature is suitable for mobile and personal computing, and communication products. the m5m29gb/t160bvp are fabricated by cmos technology for the peripheral circuits and dinor(divided bit line nor) architecture for the memory cells, and are available in in 48pin tsop(i) . features boot block m5m29gb160bvp bottom boot m5m29gt160bvp top boot other functions soft ware command control selective block lock erase suspend/resume program suspend/resume status register read alternating back ground program/erase operation between bank(i) and bank(ii) package 48-lead, 12mm x 20mm tsop (type-i) organization 1048,576 word x 16bit 2,097,152 word x 8 bit supply voltage ................................ v cc = 2.7~3.6v access time 80ns (vcc=3.3v+/-0.3v) 90ns (vcc=2.7~3.6v) power dissipation read 54 mw (max. at 5mhz) (after automatic power saving) 0.33 m w (typ.) program/erase 126 mw (max.) standby 0.33 m w (typ.) deep power down mode 0.33 m w (typ.) auto program for bank(i) program time 4ms (typ.) program unit (byte program) 1word/1byte (page program) 128word/256byte auto program for bank(ii) program time 4ms (typ.) program unit 128word/256byte auto erase erase time 40 ms (typ.) erase unit bank(i) boot block 16kword/32kbyte x 1 parameter block 16kword/32kbyte x 7 bank(ii) main block 32kword/64kbyte x 28 program/erase cycles 100kcycles ................................. ................................. ................................. ............................. ................................. ....................... .............................. ................................. ..................... .............. ...................... ......................................... ................................. application code strage digital cellular phone telecommunication mobile computing machine pda (personal digital assistance) car navigation system video game machine ........................ ........................ ......................... ......................... ................................. ................................. ................................. .......... pin configuration (top view) nc : no connection outline 48pin tsop type-i (12 x 20mm) vp(normal bend) m5m29gb/t 160bvp 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 48 47 46 45 a 16 ce# dq 0 a 0 gnd oe# byte# dq 8 dq 1 dq 9 dq 2 v cc gnd dq 10 dq 3 dq 11 dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a-1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 18 a 17 ry/by# a 11 a 10 a 15 17 18 19 20 21 22 23 24 a 13 a 12 a 14 a 9 a 8 nc rp# a 7 a 6 a 5 a 4 a 1 a 2 a 3 we# wp# 160bvp 160bvp nc a 19
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 2 m5m29gb/t160bvp (8/16 bit version) block diagram x-decoder y-decoder y-gate / sense amp. input/output buffers ce# oe# we# v cc (3.3v) gnd (0v) data inputs/outputs dq 15 /a -1 dq 14 dq 13 dq 12 dq 2 dq 1 dq 0 dq 3 wp# rp# multiplexer cui wsm status / id register 128 word page buffer main block 32kw ry/by# ready/busy output a 18 a 17 a 16 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 address inputs chip enable input output enable input write enable input write protect input reset/power down input main block 32kw bank(ii) 28 parameter block5 16kw parameter block6 16kw boot block 16kw parameter block3 16kw parameter block4 16kw parameter block1 16kw parameter block2 16kw bank(i) parameter block7 16kw a 19 byte# byte enable input
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 function deep power-down when rp# is at vil, the device is in the deep powerdown mode and its power consumption is substantially low. during read modes, the memory is deselected and the data input/output are in a high-impedance(high-z) state. after return from powerdown, the cui is reset to read array , and the status register is cleared to value 80h. during block erase or program modes, rp# low will abort either operation. memory array data of the block being altered become invalid. the m5m29gb/t160bvp includes on-chip program/erase control circuitry. the write state machine (wsm) controls block erase and byte/page program operations. operational modes are selected by the commands written to the command user interface (cui). the status register indicates the status of the wsm and when the wsm successfully completes the desired program or block erase operation. a deep powerdown mode is enabled when the rp# pin is at gnd, minimizing power consumption. read the m5m29gb/t160bvp has three read modes, which accesses to the memory array, the device identifier and the status register. the appropriate read command are required to be written to the cui. upon initial device powerup or after exit from deep powerdown, the m5m29gb/t160bvp automatically resets to read array mode. in the read array mode, low level input to ce# and oe#, high level input to we# and rp#, and address signals to the address inputs (a19-a-1:byte mode, a19-a0:word mode) output the data of the addressed location to the data input/output (d7-d0:byte mode, d15-d0:word mode). write writes to the cui enables reading of memory array data, device identifiers and reading and clearing of the status register. they also enable block erase and program. the cui is written by bringing we# to low level, while ce# is at low level and oe# is at high level. address and data are latched on the earlier rising edge of we# and ce#. standard micro-processor write timings are used. standby when ce# is at vih, the device is in the standby mode and its power consumption is reduced. data input/output are in a high-impedance(high-z) state. if the memory is deselected during block erase or program, the internal control circuits remain active and the device consume normal active power until the operation completes. alternating background operation (bgo) the m5m29gb/t160bvp allows to read array from one bank while the other bank operates in software command write cycling or the erasing / programming operation in the background. read array operation with the other bank in bgo is performed by changing the bank address without any additional command. when the bank address points the bank in software command write cycling or the erasing / programming operation, the data is read out from the status register. the access time with bgo is the same as the normal read operation. output disable when oe# is at vih, output from the devices is disabled. data input/output are in a high-impedance(high-z) state. automatic power-saving (aps) the automatic power-saving minimizes the power consumption during read mode. the device automatically turns to this mode when any addresses or ce# isn't changed more than 200ns after the last alternation. the power consumption becomes the same as the stand-by mode. while in this mode, the output data is latched and can be read out. new data is read out correctly when addresses are changed. 3
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 software command definitions the device operations are selected by writing specific software command into the command user interface. read array command (ffh) the device is in read array mode on initial device power up and after exit from deep powerdown, or by writing ffh to the command user interface. after starting the internal operation the device is set to the read status register mode automatically. read device identifier command (90h) it can normally read device identifier codes when read device identifier code command(90h) is written to the command latch. following the command write, the manufacturer code and the device code can be read from address 00000h and 00001h, respectively. read status register command (70h) the status register is read after writing the read status register command of 70h to the command user interface. also, after starting the internal operation the device is set to the read status register mode automatically. the contents of status register are latched on the later falling edge of oe# or ce#. so ce# or oe# must be toggled every status read. clear status register command (50h) the erase status, program status and block status bits are set to "1"s by the write state machine and can only be reset by the clear status register command of 50h. these bits indicates various failure conditions. block erase / confirm command (20h/d0h) automated block erase is initiated by writing the block erase command of 20h followed by the confirm command of d0h. an address within the block to be erased is required. the wsm executes iterative erase pulse application and erase verify operation. program commands a)word/byte program (40h) word/byte program is executed by a two-command sequence. the word/byte program setup command of 40h is written to the command interface, followed by a second write specifying the address and data to be written. the wsm controls the program pulse application and verify operation. the word/byte program command is valid for only bank(i). data protection the m5m29gb/t160bvp provides selectable block locking of memory blocks. each block has an associated nonvolatile lock-bit which determines the lock status of the block. in addition, the m5m29gb/t160bvp has a master write protect pin (wp#) which prevents any modifications to memory blocks whose lock-bits are set to "0", when wp# is low. when wp# is high, all blocks can be programmed or erased regardless of the state of the lock-bits, and the lock-bits are cleared to "1" by erase. see the block locking table on p.9 for details. power supply voltage when the power supply voltage (vcc) is less than v lko, low v cc lock-out voltage, the device is set to the read-only mode. regarding dc electrical characteristics of v lko, see p.10 a delay time of 2 us is required before any device operation is initiated. the delay time is measured from the time vcc reaches vccmin (2.7v). during power up, rp#=gnd is recommended. falling in busy status is not recommended for possibility of damaging the device. memory organization the m5m29gb/t160bvp has one 32kbyte boot block, seven 32kbyte parameter blocks, for bank(i) and twenty-eight 64kbyte main blocks for bank(ii). a block is erased independently of other blocks in the array. suspend/resume command (b0h/d0h) writing the suspend command of b0h during block erase operation interrupts the block erase operation and allows read out from another block of memory. writing the suspend command of b0h during program operation interrupts the program operation and allows read out from another block of memory. the bank address is required when writing the suspend/resume command. the device continues to output status register data when read, after the suspend command is written to it. polling the wsm status and suspend status bits will determine when the erase operation or program operation has been suspended. at this point, writing of the read array command to the cui enables reading data from blocks other than that which is suspended. when the resume command of d0h is written to the cui, the wsm will continue with the erase or program processes. 4 b)page program for data blocks (41h) page program for bank(i) and bank(ii) allows fast programming of 128words/256bytes of data. writing of 41h initiates the page program operation for the data area. from 2nd cycle to 257th cycle (byte mode)129th cycle (word mode), write data must be serially inputted. address a6-a0,a-1 (byte mode) / a6-a0 (word mode) have to be incremented from 00h to 7fh/ffh. after completion of data loading, the wsm controls the program pulse application and verify operation. c)single data load to page buffer (74h) / page buffer to flash (0eh/d0h) single data load to the page buffer is performed by writing 74h followed by a second write specifying the column address and data. distinct data up to 256byte/128word can be loaded to the page buffer by this two-command sequence. on the other hand, all of the loaded data to the page buffer is programed simultaneously by writing page buffer to flash command of 0eh followed by the confirm command of d0h. after completion of programing the data on the page buffer is cleared automatically. this command is valid for only bank(i) alike word/byte program. clear page buffer command (55h) loaded data to the page buffer is cleared by writing the clear page buffer command of 55h followed by the confirm command of d0h. this command is valid for clearing data loaded by single data load to page buffer command.
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 m 5 m 29g t 160b vp operating voltage : 29g : 2.7 - 3.6v standard / bgo type 29w : 1.65 - 2.2v standard / bgo type boot block : t : top boot b : bottom boot package : vp : 48pin tsop(i) 12mm x 20mm (nomal pinout) wg: csp ball pitch 0.75mm,6x8 array, 7mm x 8.5mm density/write protect/ word organizetion: mitsubishi 16m flash memory type name 5 160b : 16m wp#, x8/x16 161b : 16m wp1# & wp2#, x16
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 6 m5m29gt160bvp memory map bank(i) bank(ii) 16kword boot block 35 16kword parameter block 34 32kword main block 27 32kword main block 26 32kword main block 25 32kword main block 24 32kword main block 23 32kword main block 22 32kword main block 21 32kword main block 20 32kword main block 19 32kword main block 18 32kword main block 17 32kword main block 16 32kword main block 15 32kword main block 14 32kword main block 13 32kword main block 12 32kword main block 11 32kword main block 10 32kword main block 9 32kword main block 8 32kword main block 7 32kword main block 6 32kword main block 5 32kword main block 4 32kword main block 3 32kword main block 2 32kword main block 1 32kword main block 0 16kword parameter block 33 16kword parameter block 32 16kword parameter block 31 16kword parameter block 30 16kword parameter block 29 16kword parameter block 28 memory organization a 19 -a -1 (byte mode) a 19 -a 0 (word mode) m5m29gb160bvp memory map 32kword main block 35 32kword main block 34 32kword main block 33 32kword main block 32 32kword main block 31 32kword main block 30 32kword main block 29 32kword main block 28 32kword main block 27 32kword main block 26 32kword main block 25 32kword main block 24 32kword main block 23 32kword main block 22 bank(ii) 32kword main block 21 32kword main block 20 32kword main block 19 32kword main block 18 32kword main block 17 32kword main block 16 32kword main block 15 32kword main block 14 32kword main block 13 32kword main block 12 32kword main block 11 32kword main block 10 32kword main block 9 32kword main block 8 bank(i) 16kword parameter block 1 16kword boot block 0 16kword parameter block 2 16kword parameter block 3 16kword parameter block 4 16kword parameter block 5 16kword parameter block 6 16kword parameter block 7 x8 ( bytemode) x16 ( wordmode) f8000h-fffffh f0000h-f7fffh e8000h-effffh e0000h-e7fffh d8000h-dffffh d0000h-d7fffh c8000h-cffffh c0000h-c7fffh b8000h-bffffh b0000h-b7fffh a8000h-affffh a0000h-a7fffh 98000h-9ffffh 90000h-97fffh 00000h-03fffh 18000h-1bfffh 14000h-17fffh 10000h-13fffh 0c000h-0ffffh 08000h-0bfffh 04000h-07fffh 1c000h-1ffffh 20000h-27fffh 28000h-2ffffh 30000h-37fffh 38000h-3ffffh 40000h-47fffh 48000h-4ffffh 50000h-57fffh 58000h-5ffffh 60000h-67fffh 68000h-6ffffh 70000h-77fffh 78000h-7ffffh 80000h-87fffh 88000h-8ffffh 00000h-07fffh 30000h-37fffh 28000h-2ffffh 20000h-27fffh 18000h-1ffffh 10000h-17fffh 08000h-0ffffh 38000h-3ffffh 40000h-4ffffh 50000h-5ffffh 60000h-6ffffh 70000h-7ffffh 80000h-8ffffh 90000h-9ffffh a0000h-affffh b0000h-bffffh c0000h-cffffh d0000h-dffffh e0000h-effffh f0000h-fffffh 100000h-10ffffh 110000h-1fffffh 120000h-12ffffh 130000h-13ffffh 140000h-14ffffh 150000h-15ffffh 160000h-16ffffh 170000h-17ffffh 180000h-18ffffh 190000h-19ffffh 1a0000h-1affffh 1b0000h-1bffffh 1c0000h-1cffffh 1d0000h-1dffffh 1e0000h-1effffh 1f0000h-1fffffh x8 ( bytemode) x16 ( wordmode) fc000h-fffffh f8000h-fbfffh f4000h-f7fffh f0000h-f3fffh ec000h-effffh e8000h-ebfffh e4000h-e7fffh e0000h-e3fffh d8000h-dffffh d0000h-d7fffh c8000h-cffffh c0000h-c7fffh b8000h-bffffh b0000h-b7fffh 00000h-07fffh 30000h-37fffh 28000h-2ffffh 20000h-27fffh 18000h-1ffffh 10000h-17fffh 08000h-0ffffh 38000h-3ffffh 40000h-47fffh 48000h-4ffffh 50000h-57fffh 58000h-5ffffh 60000h-67fffh 68000h-6ffffh 70000h-77fffh 78000h-7ffffh 80000h-87fffh 88000h-8ffffh 90000h-97fffh 98000h-9ffffh a0000h-a7fffh a8000h-affffh 00000h-0ffffh 60000h-6ffffh 50000h-5ffffh 40000h-4ffffh 30000h-3ffffh 20000h-2ffffh 10000h-1ffffh 70000h-7ffffh 80000h-8ffffh 90000h-9ffffh a0000h-affffh b0000h-bffffh c0000h-cffffh d0000h-dffffh e0000h-effffh f0000h-fffffh 100000h-10ffffh 140000h-14ffffh 150000h-15ffffh 160000h-16ffffh 170000h-17ffffh 180000h-18ffffh 190000h-19ffffh 1a0000h-1affffh 1b0000h-1bffffh 1c0000h-1c7fffh 1c8000h-1cffffh 1d0000h-1d7fffh 1d8000h-1dffffh 1e0000h-1e7fffh 1e8000h-1effffh 1f0000h-1f7fffh 1f8000h-1fffffh 110000h-11ffffh 120000h-12ffffh 130000h-13ffffh a 19 -a -1 (byte mode) a 19 -a 0 (word mode)
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 7 1) x at ry/by# is v ol or v oh(hi-z) . *the ry/by# is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy p erforming an operation. a pull-up resistor of 10k-100k ohms is required to allow the ry/by# signal to transition high indicating a ready wsm conditio n. 2) x can be v ih or v il for control pins. bus operations bus operations for word-wide mode 1) mode array status register identifier code stand by program erase write read pins ce# oe# we# v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il data out status register data identifier code hi-z hi-z command/data in command output disable deep power down others rp# v ih v ih v ih v ih v ih v ih v ih ry/by# v oh (hi-z) x x x x x x v il v ih x v il x hi-z v ih v il x command dq 0-15 2) v ih lock bit status v il v il v ih lock bit data (dq 6 )x v oh (hi-z) v oh (hi-z) bus operations for byte-wide mode 1) mode array status register identifier code stand by program erase write read pins ce# oe# we# dq 0-7 v il v il v il v il v ih v il v il v il v il v il v ih x v ih v ih v ih v ih v ih v ih x v il v il data out status register data identifier code hi-z hi-z command/data in command output disable deep power down others rp# v ih v ih v ih v ih v ih v ih v ih ry/by# x x x x x x v il v ih x v il x hi-z v ih v il x command 2) lock bit status v il v il v ih v ih lock bit data (dq 6 ) x v oh (hi-z) v oh (hi-z) v oh (hi-z)
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 software command definition command list 1) in the word-wide version(byte#=h), upper byte data (dq8-dq15) is ignored. 2) ia=id code address : a0=vil (manufacturer's code) : a0=vih (device code), id=id code 3) bank = bank address (bank(i) or bank(ii)) : a19-a17. 4) srd = status register data 5) byte/word program, single data load and page buffer to flash command is valid for only bank(i). 6) wa = write address,wd = write data 7) wa0,wan=write address, wd0,wdn=write data. byte mode : write address and write data must be provided sequentially from 00h to ffh for a6-a0,a-1. page size is 256byte (256byte x 8bit), and also a19-a7(block address, page address) must be valid. word mode : write address and write data must be provided sequentially from 00h to 7fh for a6-a0. page size is 128word (128 word x 16bit). and also a19-a7(block address, page address) must be valid. 8) wa = write address : upper page address, a19-a7(block address, page address) must be valid. 9) ba = block address : ba = block address : a19-a14(bank1) a19-a15(bank2) 10) dq6 provides block lock status, dq6 = 1 : block unlock, dq6 = 0 : block locked. 8 read array ffh x write 1st bus cycle 2nd bus cycle command device identifier 90h x write id ia read read status register 70h write srd read clear status register 50h x write 2) 4) 2) page program write 41h block erase / confirm suspend resume 7) read lock bit status lock bit program / confirm erase all unlocked blocks write write 20h bank write d0h write b0h bank write 71h x write 9) write write a7h 77h d0h write read ba xd0h d0h dq6 byte/word program 5) write 40h write wd0 write 7) 7) wd 10) single data load to page buffer page buffer to flash write write 74h write wd wa 0eh write d0h 3) clear page buffer 55h x write write x d0h 5) 5) bank bank bank(i) wa bank bank ba bank x 3rd ~257th bus cycles ( byte mode ) wdn write 7) 7) wan wa0 3rd ~129th bus cycles ( word mode ) 1) 1) address mode data address mode data address mode data 1) (dq15-0) (dq7-0) 1) 1) 1) wa 6) 8) 6) (dq15-0) (dq7-0) (dq15-0) (dq7-0) ba 5) bank(i) 5) bank(i) 5)
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 9 *the ry/by# is an open drain output pin and indicates status of the internal wsm. when low,it indicates that the wsm is busy p erforming an operation. a pull-up resistor of 10k-100k ohms is required to allow the ry/by# signal to transition high indicating a ready wsm conditio n. status register status erase status program status definition symbol (dq 5 ) (dq 4 ) write state machine status (dq 7 ) (dq 6 ) (dq 1 ) (dq 0 ) (dq 3 ) (dq 2 ) "1" "0" ready busy suspended operation in progress / completed error successful error successful sr.5 sr.4 sr.7 sr.6 sr.1 sr.0 sr.3 sr.2 block status after program reserved - suspend status error successful - *dq3 indicates the block status after the page programming, byte/word programming and page buffer to flash. when dq3 is "1", th e page has the over-programed cell . if over-program occurs, the device is block fail. however if dq3 is "1", please try the block erase to th e block. the block may revive. reserved reserved -- -- block locking deep power down mode write protection provided locked lock bit (internally) x bank(i) lock bit boot parameter data locked locked locked note bank(ii) v il rp# wp# x all blocks unlocked 0 1 x locked locked unlocked unlocked unlocked unlocked locked locked locked unlocked unlocked locked v ih v il v ih 160b 1) dq 6 provides lock status of each block after writing the read lock status command (71h). wp# pins must not be switched during performing erase / write operations or wsm busy (wsms = 0). 2) erase/write command for locked blocks is aborted. at this time read mode is not array read mode but status read mode and 00b0h is read. please issue clear status register command plus read array command to change the mode from status read mode to array read mode.
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 10 capacitance symbol parameter test conditions pf pf unit max 8 12 typ min limits ta = 25 c, f = 1mhz, v in = v out = 0v input capacitance (address, control pins) output capacitance c in c out 1) minimum dc voltage is -0.5v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins is v cc +0.5v which, during transitions, may overshoot to v cc +1.5v for periods <20ns. absolute maximum ratings conditions parameter with respect to ground symbol v cc all input or output voltage v i1 v cc voltage 1) unit v v min max 4.6 -0.2 ambient temperature temperature under bias t a t bs storage temperature t stg c c c 85 -50 95 -65 125 output short circuit current i out ma 100 -0.6 4.6 -40 all currents are in rms unless otherwise noted. 1) typical values at vcc=3.3v, ta=25 c 2) to protect against initiation of write cycle during vcc power-up/ down, a write cycle is locked out for vcc less than v lko. if vcc is less than v lko, write state machine is reset to read mode. when the write state machine is in busy state, if vcc is less than v lko , the alteration of memory contents may occur. dc electrical characteristics (ta = -40~ 85 c, vcc = 2.7v ~ 3.6v, unless otherwise noted) symbol parameter max typ1) limits min test conditions unit v cc standby current i lo 10 output leakage current m a 0v v out v cc i li input leakage current m a 0v v in v cc 1 v cc deep powerdown current i cc3 v cc program current ma 35 v cc = 3.6v, v in =v il /v ih , ce# = rp# =wp# = v ih i cc4 v cc erase current ma 35 v cc = 3.6v, v in =v il /v ih , ce# = rp# =wp# = v ih output high voltage v v ol output low voltage v i ol = 4.0ma 0.45 vcc+0.5 v ih input high voltage v 2.0 0.8 v il input low voltage C 0.5 v oh1 i oh = C2.0ma 0.85vcc v v oh2 i oh = C100 m a vccC0.4 v v lko low v cc lock-out voltage 2) 1.5 2.2 v i cc5 v cc suspend current 200 v cc = 3.6v, v in =v il /v ih , ce# = rp# =wp# = v ih m a i sb2 5 v cc = 3.6v, v in =gnd or v cc , ce# = rp# = wp#= v cc 0.3v m a 0.1 15 ma i cc1 v cc read current for word or byte v cc = 3.6v, v in =v il /v ih , ce# = v il , rp#=oe#=v ih , i out = 0ma 8 i sb1 v cc = 3.6v, v in =v il /v ih , ce# = rp# =wp# = v ih m a 200 50 i cc2 15 ma v cc write current for word or byte v cc = 3.6v,v in =v il /v ih , ce# =we#= v il , rp#=oe#=v ih v cc = 3.6v, v in =v il /v ih , rp# = v il m a 15 5 i sb3 m a 0.1 i sb4 v cc = 3.6v, v in =gnd or v cc , rp# =gnd 0.3v 5 5mhz 4 2 1mhz device identifier code in the word-wide mode, the upper data(d 15-8) is "0". code manufacturer code pins hex. data 1ch dq 0 0 a 0 v il dq 1 0 dq 2 1 dq 3 1 dq 4 1 dq 5 dq 6 0 dq 7 0 device code (-t160bvp) a0h v ih 00 1 device code (-b160bvp) v ih 10 0 1 1 0 0 0 0 0 0 0 a1h 0 1
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 11 read-only mode ac electrical characteristics (ta = -40 ~85 c) read timing parameters during command write operations mode are the same as during read-only operations mode. typical values at vcc=3.3v, ta=25 c ac electrical characteristics (ta = -40 ~85 c) write mode (we# control) symbol parameter write cycle time data hold time data set-up time address hold time address set-up time t avav t whdx t dvwh t whax t avwh t wc t dh t ds t ah t as limits 80 50 50 max min typ 0 0 unit ns ns ns ns ns 90 50 50 max min typ 0 0 write pulse width chip enable hold time chip enable set-up time write pulse width high block lockhold from valid srd duration of auto-program operation duration of auto-block erase operation block lock set-up to write enable high t wlwh t wheh t elwl t whwl t qvph t whrh1 t whrh2 t phhwh t wp t ch t cs t wph t bls t blh t dap t dae oe# hold to we# low t ghwl t ghwl 4 40 80 600 60 0 30 0 80 0 0 ns ns ns ns ns ms ms ns 4 40 80 600 60 0 30 0 90 0 ns 0 symbol parameter t a (ad) address access time t avqv t clz chip enable to output in low-z t elqx t a (ce) chip enable access time t elqv t a (oe) output enable access time t glqv t df(ce) chip enable high to output in high z t ehqz t rc read cycle time t avav t olz t glqx output enable to output in low-z t df(oe) t ghqz output enable high to output in high z t phz rp# low to output high-z t plqz unit ns ns ns ns ns ns ns ns ns 80 0 80 30 25 80 0 25 150 max min typ 90 0 90 30 25 90 0 25 150 max min typ limits speed item: -80 vcc=2.7~3.6v vcc=3.3v+/-0.3v speed item: -80 vcc=2.7~3.6v vcc=3.3v+/-0.3v ns ns 10 10 30 30 oe# hold from we# high t whgl t oeh latency between read and write ffh or 71h - t re timing measurements are made under ac waveforms for read operations. t whgl oe# hold from we# high t oeh t bad t avfl/h rp# recovery to ce# low ns ns ns t ps t phel 10 0 150 10 0 150 t elfl/h f-ce# low to byte# high or low t bcd t oh output hold from ce#, oe#, addresses t oh address to byte# high or low 5 5 5 5 t a(byte) byte# access time t fl/hqv t bhz byte# low to output high-z t flqz 80 25 90 25 byte enable high or low set-up time t fl/hwh t bs t whfl/h t bh byte enable high or low hold time 50 80 50 90 ns ns ns ns ns ns 0 rp# high recovery to write enable low t phwl t ps 150 ns 150 write enable high to f-ry/by# low t whrl t whrl 90 ns 90
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 12 during power up/down, by the noise pulses on control pins, the device has possibility of accidental erasure or programming. the device must be protected against initiation of write cycle for memory contents during power up/down. the delay time of min.2 m sec is always required before read operation or write operation is initiated from the time vcc reaches vccmin during power up/d own. by holding rp# vil, the contents of memory is protected during vcc power up/down. during power up, rp# must be held vil for min.2 m s from the time vcc reaches vccmin. during power down, rp# must be held vil until vcc reaches gnd. rp# doesn't have latch mode ,therefore rp# must be held vih during read operation or erase/program operation. erase and program performance block erase time main block write time (page mode) page write time parameter ms sec ms unit typ 4 1.0 40 max 80 1.8 600 min program suspend latency / erase suspend time program suspend latency erase suspend time parameter unit typ max 15 15 min m s m s please see page 19. vcc power up / down timing symbol unit typ 2 max min t vcs parameter rp# =v ih set-up time from vccmin m s please see page 12. read timing parameters during command write operation mode are the same as during read-only operation mode. typical values at vcc=3.3v, ta=25 c ac electrical characteristics (ta = -40 ~ 85 c) write mode (ce# control) symbol parameter write cycle time data hold time data set-up time address hold time address set-up time ce# pulse width write enable hold time write enable set-up time t avav t ehdx t dvwh t ehax t avwh t eleh t ehwh t wlel t wc t dh t ds t ah t as t cep t wh t ws 80 50 50 60 0 0 max min typ 0 0 unit ns ns ns ns ns ns ns ns 90 50 50 60 0 0 max min typ 0 0 block lockhold from valid srd duration of auto-program operation duration of auto-block erase operation block lock set-up to write enable high t qvph t ehrh1 t ehrh2 t phheh t bls t blh t dap t dae oe# hold to ce# low t ghel t ghel 4 40 80 600 0 80 80 ns ns ms ms ns 4 40 80 600 ce# pulse width high t ehel t ceph 30 30 0 90 ns 90 limits speed item: -80 vcc=2.7~3.6v vcc=3.3v+/-0.3v 10 10 30 30 oe# hold from ce# high t ehgl t oeh latency between read and write ffh or 71h - t re ns ns byte enable high or low set-up time t fl/hwh t bs t whfl/h t bh byte enable high or low hold time 50 80 50 90 ns ns rp# high recovery to write enable low t phwl t ps 150 ns 150 f-ce# high to f-ry/by# low t ehrl t ehrl 90 ns 90
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 13 3.3v gnd v cc vcc power up / down timing v ih v il rp# read /write inhibit t vcs v ih v il ce# v ih v il we# t ps t ps read /write inhibit read /write inhibit test conditions for ac characteristics input voltage : v il = 0v, v ih = 3.0v input rise and fall times : 5ns reference voltage at timing measurement : 1.5v output load : 1ttl gate + cl(30pf) or ac waveforms for read operation and test conditions output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses ce# oe# we# data address valid t oh t olz t a (ce) t oeh t clz t a (ad) t a (oe) high-z dut 3.3k w 1n914 1.3v c l =30pf v ih v il rp# t ps t df(ce) t phz
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 v ih v il v ih v il v ih v il v ih v il addresses (a 0 - a 19 ,a -1 *) address valid ce# byte# data (d 0 - d 7 ) byte ac waveforms for read operation t a(ad) high-z v ih v il data (d 8 - d 14 ) high-z v ih v il d 15 / a -1 t a(byte) t bhz valid valid output valid valid a -1 d 15 a -1 v ih v il oe# when byte#=v ih , ce#=oe#=v il , d 15 /a -1 is output status. at this time, input signal must not be applied. address valid t a(ad) t a(ce) t a(oe) t a(byte) t bcd t bad t clz t olz t bad t oh t df(oe) t df(ce) 14 ac waveforms for write ffh or 71h and read operation output valid high-z t df(oe) t rc v ih v il v ih v il v ih v il v ih v il v oh v ol addresses ce# oe# we# data address valid t oh t olz t a (ce) t re t clz t a (ad) t a (oe) high-z v ih v il rp# t ps t df(ce) t phz valid ffh or 71h in the case of use ce# is low fixed, it is allowed to define a timming specification of tre from rising edge of we# to falling edge of oe#, and valid data is read after spec of tre+ta(ce). (this is only for ffh,71h program and read)
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 15 ac waveforms for page program operation (we# control) 41h din t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il address valid ce# oe# we# data ry/by# t ah v ih v oh v ol v il 00h ffh 01h~feh t as din srd din v ih v il t oeh t dap t whrl program read status register write read array command ffh 7fh 01h~7eh 00h t a(ce) t a(oe) v il v ih v il t blh t bls t ps v ih rp# bank address valid the other bank address valid valid dout t oeh t ghwl t a(oe) t a(ce) valid a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) wp# bank address valid v ih byte# v il t bs t bh ac waveforms for page program operation (ce# control) 41h din t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il address valid ce# oe# we# data t ah v ih v il 00h ffh 01h~feh t as din srd din v ih v il t oeh t dap program read status register write read array command ffh 7fh 01h~7eh 00h t a(ce) t a(oe) bank address valid valid valid valid dout t a(ce) t oeh t ghel t a(oe) the other bank address ry/by# v oh v ol t ehrl t ps v ih v il rp# v ih v il wp# t blh t bls a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) bank address valid v ih byte# v il t bs t bh
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 16 ac waveforms for byte / word program operation (we# control) (to only bank(i)) write read array command read status register v ih v il address valid program v ih v il v ih v il v ih v ih ce# oe# we# data ry/by# v il v ih v il v ih v il rp# v ih v il wp# v il 40h din t cs t ch t wph t wp t ds t ps t dap t whrl t oeh t a(ce) t a(oe) t blh t dh srd ffh t ah t as t wc t bls bank(i) address valid bank address valid v ih byte# v il t bh t bs ac waveforms for byte / word program operation (ce# control) (to only bank(i)) write read array command read status register v ih v il address valid program v ih v il v ih v il v ih v ih ce# oe# we# data ry/by# v il v ih v il v ih v il rp# v ih v il v il 40h din t ws t wh t cep t ds t dap t ehrl t oeh t a(ce) t a(oe) t blh t dh srd ffh t ah t as t wc t bls bank(i) address valid wp# bank address valid v ih byte# v il t ps t bh t bs addresses addresses
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 17 ac waveforms for erase operations (we# control ) 20h d0h t wph t wp t ds t dh t cs t ch t wc v ih v il v ih v il v ih v il v ih v il ry/by# t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dae t whrl address valid erase read status register write read array command ce# oe# we# data t a(oe) t a(ce) bank address valid v il v ih v il t ps v ih rp# wp# bank address valid v ih byte# v il t bs t bh t blh t bls ac waveforms for erase operations (ce# control) 20h d0h t ceph t cep t ds t dh t ws t wh t wc v ih v il v ih v il v ih v il v ih v il ry/by# t ah v ih v oh v ol v il addresses t as ffh srd t oeh t dae t ehrl address valid erase read status register write read array command ce# oe# we# data t a(oe) t a(ce) bank address valid v il v ih v il t ps v ih rp# wp# bank address valid v ih byte# v il t bh t blh t bs t bls
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 18 ac waveforms for page program operation with bgo (we# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih address valid ce# oe# we# data ry/by# v ih v il v il 00h 01h~feh ffh v ih v il 7fh 01h~7eh 00h v il 41h din dout din din srd valid valid valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout program data to one bank change bank address a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) bank address valid ac waveforms for page program operation with bgo (ce# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih address valid ce# oe# we# data ry/by# v ih v il v il 00h 01h~feh ffh v ih v il 7fh 01h~7eh 00h v il 41h din dout din din srd valid valid valid valid t wc t as t ah t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout program data to one bank change bank address a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) bank address valid
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 19 ac waveforms for byte / word program operation with bgo (we# control) array read from bank(ii) with bgo v ih v il v ih v il v ih v il v ih v ih address valid ce# oe# we# data ry/by# v ih v il v il v ih v il v il 40h din dout srd valid valid valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout program data to bank(i) valid read status register change bank address a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) bank address valid ac waveforms for byte / word program operation with bgo (ce# control) change bank address array read from bank(ii) with bgo v ih v il v ih v il v ih v il v ih v ih ce# oe# we# data ry/by# v ih v il v il v ih v il v il 40h din dout srd valid valid valid valid t wc t as t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout program data to bank(i) valid address valid read status register a19~a7 byte#=vil (a6~a-1) byte#=vih (a6 ~a0) bank address valid
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 20 ac waveforms for block erase operation with bgo (we# control) array read from the other bank with bgo v ih v il v ih v il v ih v il v ih v ih addresses address valid ce# oe# we# data ry/by# v il v ih v il v il 20h d0h dout srd valid valid t wc t as t ah t cs t ch t wph t wp t ds t dh t whrl t a(ce) t a(oe) t oeh dout block erase in one bank read status register change bank address bank address valid ac waveforms for block erase operation with bgo (ce# control) v ih v il v ih v il v ih v il v ih v ih ce# oe# we# data ry/by# v il v ih v il v il 20h d0h dout srd valid valid t wc t as t ws t ch t ceph t cep t ds t dh t ehrl t a(ce) t a(oe) t oeh dout address valid t ah read data from the other bank with bgo addresses block erase in one bank read status register change bank address bank address valid
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 21 ac waveforms for suspend operation (ce# control ) b0h v ih v il v ih v il v ih v il v ih v il ry/by# v ih v oh v ol v il addresses t as t oeh program suspend latency t cep bank address valid read status register ce# oe# we# data t a(oe) t a(ce) bank address valid v il v ih v il v ih rp# t bls valid srd t blh t ah t ws t wh wp# s.r.6,7=1 ac waveforms for suspend operation (we# control ) b0h t wp t cs t ch v ih v il v ih v il v ih v il v ih v il ry/by# v ih v oh v ol v il addresses t as t oeh bank address valid read status register ce# oe# we# data t a(oe) t a(ce) bank address valid v il v ih v il v ih rp# t bls t blh t ah valid srd program suspend latency wp# s.r.6,7=1
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 22 full status check procedure sr.5 = 0 ? sr.4 = 0 ? sr.4 =1 and sr.5 =1 ? successful (block erase, program) yes yes yes no status register read command sequence error no block erase error no program error (block) write 77h write d0h block address lock bit program flow chart sr.4 = 0 ? lock bit program successful yes yes no no start lock bit program failed sr.7 = 1 ? sr.3 = 0 ? yes no program error (page, lock bit) page program flow chart start write 41h full status check if desired page program completed yes n = 0 n = n+1 write address n, data n yes sr.7 = 1 ? n = ffh ? or n = 7fh ? no write b0h ? yes no suspend loop write d0h yes no status register read byte program flow chart start write 40h full status check if desired page program completed yes write address , data sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read * byte program is admitted to only bank(i).
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 23 suspend / resume flow chart start write b0h operation resumed sr.6 =1? yes no write ffh read array data done reading ? no yes write d0h suspend resume block erase flow chart start write 20h write d0h block address full status check if desired yes sr.7 = 1 ? write b0h ? yes no suspend loop write d0h yes no status register read block erase completed status register read sr.7 = 1? yes no program / erase completed * the bank address is required when writing this command. also, there is no need to suspend the erase or program operation when reading data from the other bank. please use bgo function. single data load to page buffer start write 74h full status check if desired page buffer to flash completed write address , data write b0h ? yes no suspend loop write d0h yes no status register read write 0eh write d0h page address sr.7 = 1 ? yes done loading? no single data load to page buffer completed page buffer to flash start clear page buffer start write 55h write d0h page buffer clear completed
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 24 operation status and effective command page program setup lock bit program setup block erase setup setup state read/standby state other erase & verify read status register b0h d0h b0h d0h 50h 41h 77h 20h a7h suspend state read array read status register ffh 70h 70h read status register read device identifier read lock status ffh 70h 90h 70h 90h ffh ffh 71h 70h 71h 90h read array other other d0h d0h d0h wdi i=0-255 erase all unlocked blocks setup program & verify read status register 71h clear status register ready read array (from the other bank) change bank address change bank address read state with bgo 40h byte program setup wd 0eh d0h single data load to page buffer setup 74h wd other page buffer to flash setup internal state clear page buffer setup 55h d0h
mitsubishi lsis 16,777,216-bit (2097,152-word by 8-bit / 1048,576-word by16-bit) cmos 3.3v-only, block erase flash memory m5m29gb/t160bvp-80 sep 1999. rev2.0 e z 1 z lp a3 l h d d e c l1 a 2 a 1 a b q l 2 m d b 2 e 18.6 0.225 0.9 10 0 0.1 0.8 0.6 0.5 0.4 20.2 20.0 19.8 0.5 12.1 12.0 11.9 18.5 18.4 18.3 0.175 0.125 0.105 0.3 0.2 0.15 1.0 0.2 0.125 0.05 1.2 0.1 0.4 0.75 0.6 0.25 0.45 0.25 1 24 48 25 detail g detail f m x y f g d 48p3e-c plastic 48pin 12x20mm tsop(i) cu alloy lead material eiaj package code jedec code weight(g) tsop i 48-p-1220-0.50 z x lp dimension in millimeters max nom min symbol z 1 recommended mount pad a 1 l e e d c b 2 a a d h 1 l 2 l m 2 b y q a3 package dimensions 48p3e (48pin 12 x 20 mm tsop(i)) 25

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